Semiconductor device and production method thereof

ABSTRACT

A semiconductor device and a production method thereof capable of reducing warps of a semiconductor wafer when packaging at a wafer level in a SiP type semiconductor device, is configured that an insulating layer is formed by stacking a plurality of resin layers on a semiconductor chip formed with an electronic circuit, wiring layers are buried in the insulating layer and electrically connected to electrodes, and formation areas of the plurality of resin layers become gradually smaller from an area of an upper surface of the semiconductor chip as they get farther from the semiconductor chip, so that a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape.

CROSS REFERENCE TO RELATED APPLICATION

This application is a Reissue of U.S. Pat. No. 7,170,175, issued Jan.30, 2007, which claims priority to Japanese Application No.P2003-335703, filed Sep. 26, 2003, the entire contents of which isincorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device a the productionmethod therefor, and, particularly to a semiconductor device of a typecalled a system-in-package (SiP), which is packaged at a wafer level,and a production method therefor.

2. Description of the Related Art

Demands for more compact, thinner and lighter portable electronicdevices, such as digital video cameras, digital cellular phones, andnotebook computers, only get stronger. To respond thereto, seven tenthsof a reduction has been realized in three years in a recent VLSI andother semiconductor devices, while studies and developments have beenmade on the significant issue of how to improve packaging density ofcomponents on a mounting board (printed wiring board) in an electroniccircuit device wherein such a semiconductor device is mounted on aprinted wiring board.

For example, the package type of a semiconductor device has shifted fromthe lead-inserted type, such as a dual inline package (DIP), to thesurface-mounted type. Furthermore, a flip-chip mounting method forproviding a bump (protruding electrode) made of solder or gold on a padelectrode of a semiconductor chip and connecting to the wiring board viathe bump with the surface facing downward has been developed.

In the above semiconductor device, when forming multilayer wiring, alsocalled rewiring layers, on the semiconductor substrate (chip), forexample, an insulating layer is formed to be a film thickness of 1 μm orless on a surface of a semiconductor wafer formed with a transistor andother semiconductor elements by the chemical vapor deposition (CVD)method, the sputtering method, the thermal oxidization method or thespin coating method, etc., and dicing processing is performed to obtaina small piece of semiconductor device.

In the above production method, even when a step is generated on theinsulating layer and warps arise on the wafer, it is sufficient to payattention only to the blade and chipping at the dicing stage and it isunnecessary to pay attention to the step disconnection of a resist andwarps of the wafer.

Furthermore, development has been advanced to a complicated type ofpackage called a system-in-package (SiP) wherein a passive element, suchas a coil, and other semiconductor chips are buried in an interlayer ofan insulating layer for insulating rewiring layers formed on asemiconductor substrate (chip) and packaged at a wafer level.

As a production method of the SiP, for example, a method of forming asthe insulating layer of the rewiring layers an insulating layer made ofa polyimide resin and an epoxy resin, etc., to be a film thickness of 10μm or less by the spin coating method on the surface of thesemiconductor wafer formed with a transistor and other semiconductorelement and performing dicing processing to obtain a small piece hasbeen widely used.

Here, in the case where property values of the insulating layer aredifferent in an elastic modulus and a thermal expansion coefficient fromthose in the semiconductor made by silicon, etc., a method of removing aresin on a scribe line in advance and cutting on the exposed scribe lineto obtain a small piece is used.

In the production method of the SiP as above, in the case where theinsulating layer of the rewiring layers is made to be a multilayer of,for example, three layers or more, when assuming that a film thicknessof one layer is 10 μm at minimum, the thickness becomes 30 μm by puttingthe three layers together, so that it becomes relatively impossible toignore the film thickness of the insulating layer of the rewiring layerin the case where, for example, a silicon substrate is made to be asthin as 50 μm or less.

Furthermore, in the case of forming a coil and other passive elements inan interlayer of the insulation layer of the rewiring layers in the SiPstructure and in the case of burying a semiconductor chip, the filmthickness of the whole insulating layer of the rewiring layers has to be50 μm or more, and an effect given to warps of the semiconductor waferbecomes large.

When warps arise on the semiconductor wafer, an adsorbent error and aconveyance error may be caused in a production facility and breakage anda decline of the yield may also be brought. Furthermore, a disadvantageof a decline of secondary connection reliability is unfavorably causeddue to residual stress.

SUMMARY OF THE INVENTION

An object of the present invention is to prevent the arising of warps ofa semiconductor wafer when an insulating layer in rewiring layersbecomes thick in a SiP type semiconductor device, which may cause anadsorption error and a conveyance error in a production facility,breakage, a decline of the yield and a decline of secondary connectionreliability due to residual stress.

According to the present invention, there is provided a semiconductordevice comprising a semiconductor chip with a built-in electroniccircuit, having electrodes formed on a surface thereof which are takenout from the electronic circuit, an insulating layer formed of aplurality of resin layers stacked on the semiconductor chip, and awiring layer formed to be electrically connected to the electrodes andburied in the insulating layer, wherein the plurality of resin layers isformed so that as the layers get farther from the semiconductor chip,their formation areas become gradually smaller from an area of an uppersurface of the semiconductor chip, and a side surface and an uppersurface of each of the resin layers and the upper surface of thesemiconductor chip form a stepwise shape.

In the semiconductor device of the present invention, an insulatinglayer is configured by stacking a plurality of resin layers on asemiconductor chip formed with an electronic circuit, wherein a wiringlayer is buried to be electrically connected to electrodes.

Here, the plurality of resin layers has the configuration wherein thelayers' formation areas become gradually smaller from an area of anupper surface of the semiconductor chip as they get farther from thesemiconductor chip, and a side surface and an upper surface of each ofthe resin layers and the upper surface of the semiconductor chip form astepwise shape.

Also, according to the present invention, there is provided a productionmethod of a semiconductor device, including the steps of formingintegrated electronic circuits corresponding to a plurality ofsemiconductor chips on a semiconductor wafer, and forming electrodes ona surface of the semiconductor wafer by taking them out from theelectronic circuits, forming a pattern of a first resin layer on thesurface of the semiconductor wafer except for a scribe line to be adicing region, forming on the first resin layer a pattern of a firstwiring layer electrically connected to the electrodes, forming a patternof a second resin layer to cover the first resin layer and the firstwiring layer except for the scribe line, and dicing the semiconductorwafer on the scribe line, wherein in the step of forming the secondresin layer, the second resin layer is formed on a smaller area thanthat of the first resin layer, so that a side surface and an uppersurface of each of the first resin layer and the second resin layer forma stepwise shape.

In the production method of the semiconductor device of the presentinvention, electronic circuits corresponding to a plurality ofsemiconductor chips are formed to be integrated on the semiconductorwafer first, and electrodes are formed on its surface by being taken outfrom the electronic circuits.

Next, a pattern of a first resin layer is formed on a surface of thesemiconductor wafer except for a scribe line to be a dicing region, apattern of a first wiring layer is formed on the first resin layer andelectrically connected to the electrodes, and a pattern of a secondresin layer is formed to cover the first resin layer and the firstwiring layer except for the scribe line.

Next, dicing for cutting the semiconductor wafer on the scribe line isperformed.

When forming the second resin layer, it is formed to have a smaller areathan that of the first resin layer, so that a side surface and an uppersurface of each of the first resin layer and the second resin layer forma stepwise shape.

BRIEF DESCRIPTION OF DRAWINGS

These and other objects and features of the present invention willbecome clearer from the following description of the preferredembodiments given with reference to the attached drawings, in which:

FIG. 1 is a sectional view of a semiconductor device according to anembodiment of the present invention;

FIG. 2A to FIG. 2C are views of production steps of the semiconductordevice according to the embodiment of the present invention;

FIG. 3A to FIG. 3C are sectional views of production steps of thesemiconductor device according to the embodiment of the presentinvention;

FIG. 4A to FIG. 4C are sectional views of production steps of thesemiconductor device according to the embodiment of the presentinvention;

FIG. 5A to FIG. 5C are sectional views of production steps of thesemiconductor device according to the embodiment of the presentinvention; and

FIG. 6A to FIG. 6C are sectional views of production steps of thesemiconductor device according to the embodiment of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Below, an embodiment of the present invention will be explained withreference to the drawings.

FIG. 1 is a schematic sectional view of a semiconductor device accordingto the present embodiment.

On the surface of a semiconductor chip (semiconductor substrate) 10aformed with an electronic circuit including a transistor and othersemiconductor elements, electrodes (not shown) taken out from theelectronic circuit are formed. On the semiconductor substrate (chip)10a, an insulating layer configured by stacking a first resin layer 20,a second resin layer 21, a third resin layer 22 and a fourth resin layer23 is formed.

Wiring layers composed of first wiring layers (30, 31), second wiringlayers (32, 33) and third wiring layers (34, 35) are formed by beingburied in the insulating layer composed of the above stacked resinlayers. The wiring layers are formed to be electrically connected to theelectrodes taken out from the electronic circuit of the semiconductorchip 10a in a not shown part.

In the above configuration, formation areas of the first resin layer 20,the second resin layer 21, the third resin layer 22 and the fourth resinlayer 23 become gradually smaller from an area of an upper surface ofthe semiconductor chip 10a as they get farther from the semiconductorchip 10a, so that a side surface and an upper surface of each of thefirst resin layer 20, the second resin layer 21, the third resin layer22 and the fourth resin layer 23 and an upper surface of thesemiconductor chip 10a form a stepwise shape.

Each of the widths (D₁, D₂ and D₃) of exposed upper surfaces of therespective resin layers (20, 21 and 22) on the stepwise formed portionis preferably 5 μm or more, and is, for example, 5 μm. Note that a widthD₀ of an exposed part of the semiconductor chip 10a being out of thefirst resin layer 20 depends on the width of the scribe line on thesemiconductor wafer before dicing, and is, for example, 10 μm or so.When the above widths (D₁, D₂ and D₃) are 5 μm or more, coverage of aresist film covering over the scribe line becomes preferable in theproduction method.

It is also possible to form the electronic element and/or thesemiconductor chip by burying them in the insulating layer so as to beelectrically connected to the respective wiring layers.

According to the semiconductor device of the above present embodiment,in a SiP-type semiconductor device wherein an insulating layer isconfigured by stacking a plurality of resin layers on a semiconductorchip, it is configured so that formation areas of the plurality of resinlayers become gradually smaller from an area of an upper surface of thesemiconductor chip as they get farther from the semiconductor chip, anda side surface and an upper surface of each of the resin layers and theupper surface of the semiconductor chip form a stepwise shape, andconsequently, a stress imposed on the semiconductor wafer is small evenin a stage before dicing and warps are suppressed.

Next, a production method of the above semiconductor device will beexplained with reference to the drawings.

First, as shown in FIG. 2A, electronic circuits (not shown) including atransistor and other semiconductor elements and corresponding to aplurality of semiconductor chips are formed to be integrated on thesemiconductor wafer 10. Furthermore, electrodes (not shown) are formedon the surface of the semiconductor wafer 10 so as to be taken out fromthe electronic circuits.

Next, as shown in FIG. 2B, except for a scribe line SL to be a dicingregion, a pattern of the first resin layer 20 is formed, for example, tobe a film thickness of 10 μm or so on the semiconductor wafer 10.

The first resin layer is formed by using a negative photosensitive resinmaterial, such as a polyimide resin, an epoxy resin and an acrylicresin, by the spin coating method, the printing method or the CVDmethod, etc., and subjected to exposure by using a photomask, so thatregions other than the scribe line are irradiated. When using, forexample, a photosensitive polyimide resin, the exposure is performed bybroadband exposure to covering lights of a g-line, an h-line and ani-line with energy of 300 mJ/cm². In the case of an epoxy resin,exposure is performed with energy of 2000 mJ/cm².

Furthermore, development processing is performed by using a 2.38%trimethylammonium hydroxide solution as a developing solution. Due tophotosensitivity of the used resin, the scribe line SL opens in thedevelopment stage. Here, in the case of a negative photosensitive resin,as a result that curing proceeds by photoreaction, a pattern shapevaries by the exposure condition and the actual condition, but itbecomes a tapered opening shape.

The scribe line SL is formed to be a width of, for example, 78 μm.

Next, as shown in FIG. 2C, a seed layer 30 is formed all over, forexample, by the sputtering method. As a seed layer for plating copper,for example, a film of Ti/Cu is formed to be a film thickness of 160nm/600 nm.

Next, as shown in FIG. 3A, a negative or positive resist film is formedon the seed layer 30, for example, by the spin coating; pattern exposureis performed by using a photomask, so that the pattern remains onregions other than formation regions of the first wiring layer in apredetermined wiring circuit pattern; and development processing isperformed to form a pattern of the first resist film R1. The regions notformed with the first resist film R1 become formation regions of thefirst wiring layer. Since the first wiring layer is not formed on thescribe line SL, it is covered with the first resist film R1.

Next, as shown in FIG. 3B, a copper film is formed on regions other thanthe formation regions of the first resist film R1 by performingelectroforming plating processing using the seed layer 30 as oneelectrode, and a copper plating layer 31 is formed in a predeterminedwiring circuit pattern.

Next, as shown in FIG. 3C, the first resist film R1 is peeled by solventprocessing, etc. to make the copper plating layer 31 exposed. Wetetching, etc., is performed by using the copper plating layer 31 asshown in FIG. 4A, and the seed layer 30 between the copper platinglayers 31 is removed in order to insulate. As a result, the first wiringlayer composed of the seed layer 30 and the copper plating layer 31 isformed. While the first wiring layer is not shown in FIG. 4A, it isformed so as to be connected to electrodes (not shown) provided on thesurface of the semiconductor wafer 10.

Next, as shown in FIG. 4B, except for the scribe line SL to be a dicingregion and a via hole VH, a pattern of the second resin layer 21 isformed to be a film thickness of, for example, 10 μm or so on the firstwiring layer (30, 31).

The second resin layer 21 can be formed by the same means and materialas those of the first resin layer 20. In the step of forming the secondresin layer 21, the layer is formed to have a smaller area than that ofthe first resin layer 20, so that a side surface and an upper surface ofthe first resin layer 20 and the second resin layer 21 form a stepwiseshape.

On the stepwise formed portion, a width D₁ of the exposed upper surfaceof the first resin layer 20 that is out of the second resin layer 21 ispreferably 5 μm or more and is assumed to be, for example, 5 μm.

The via hole VH connected to the first wiring layer (30, 31) can beformed in the same way.

Next, as shown in FIG. 4C, a seed layer 32 is formed all over, forexample, by the sputtering method in the same way as the above.

Since the width D₁ of the exposed upper surface of the first resin layer20 that is out of the second resin layer 21 is 5 μm or more, coverage ofthe seed layer 32 covering the scribe line becomes preferable and stepdisconnection on the seed layer 32 can be prevented.

Next, as shown in FIG. 5A, a resist film is formed on the seed layer 32,for example, by spin coating and a pattern of a second resist film R2for protecting the scribe line SL and regions other than formationregions of the second wiring layer is formed.

Since the width D₁ of the exposed upper surface of the first resin layer20 that is out of the second resin layer 21 is 5 μm or more, coverage ofthe resist film R2 covering the scribe line becomes preferable and stepdisconnection on the resist film R2 can be prevented.

Next, as shown in FIG. 5B, electroforming plating processing isperformed by using the seed layer 32 as one electrode to form a copperfilm on regions other than the formation regions of the second resistfilm R2, and a copper plating layer 33 is formed in a predeterminedwiring circuit pattern.

Next, as shown in FIG. 5C, the second resist film R2 is peeled, and theseed layer 32 between the respective copper plating layer 33 is removedby etching, as shown in FIG. 6A, to form a second wiring layer composedof the seed layer 32 and the copper plating layer 33. The second wiringlayer is formed to be electrically connected to the first wiring layervia the via hole VH.

Next, as shown in FIG. 6B, by repeating the same steps as above, thethird resin layer 22 and the fourth resin layer 23 are formed in thesame way as the first resin layer 20 and the second resin layer 21, andthe third wiring layer (34, 35) is formed in the same way as the firstwiring layer (30, 31) and the second wiring layer (32, 33),respectively. The third wiring layer (34, 35) is formed to be connectedto the second wiring layer (32, 33) in the via hole.

Here, in a step of forming the third resin layer 22, the layer is formedto have a smaller area than that of the second resin layer 21, so that aside surface and an upper surface of each of the second resin layer 21and the third resin layer 22 form a stepwise shape. Also, in a step offorming the fourth resin layer 23, the layer is formed to have a smallerarea than that of the third resin layer 22, and a width (D₂, D₃) of anexposed upper surface of a lower resin layer that is out of its upperresin layer is 5 μm or more, for example 5 μm, so that a side surfaceand an upper surface of each of the third resin layer 22 and the fourthresin layer 23 form a stepwise shape.

In the above steps, the first to fourth resin layers (20, 21, 22 and 23)are not formed on the scribe line SL on the semiconductor wafer 10, andthe upper surface of the semiconductor wafer 10 is exposed.

Here, by performing a dicing step for cutting the semiconductor wafer 10into a semiconductor chip 10a along the scribe line SL by using a dicingblade B (with a blade rotation speed of 3000 rpm and a feeding speed of10 to 15 mm/second), a semiconductor device made to be a small piece, asshown in FIG. 1 , is obtained.

In the above dicing step, only the semiconductor wafer is cut and it isnot necessary to cut the resin layers; there is therefore the advantagethat it is not necessary to select a special blade, either.

In a laminated beam model obtained by putting one substrate with othersubstrate, when the temperature changes from T₀ to T₁, expansion of onesubstrate (a linear expansion coefficient α₁) becomes α₁ (T₁−T₀), andexpansion of the other substrate (a linear expansion coefficient α₂)becomes α₂ (T₁−T₀).

When assuming that the Young's modulus of one substrate is E1 and thatof the other substrate is E2 and α₁<α₂, a compression stress of¼E(α₂−α₁)(T₁−T₀) acts on the one substrate, and the same amount of anextension stress acts on the other substrate.

Accordingly, the effects of removing resin layers on the scribe line asabove are to shorten a unit length and to disperse the stresses.

EXAMPLE

In the case of forming a resin layer as four stacked layers (a filmthickness of 50 μm in total) on a semiconductor wafer, on whichsemiconductor chips of 3 mm square are integrated, warps of thesemiconductor wafer (a distance of one end portion floating from a planewhen pressing the other end of the wafer on the plane) could be reducedby 200 μm by applying the present embodiment.

As explained above, in the production method of a semiconductor deviceaccording to the present embodiment, resin layers on the scribe line areremoved when stacking the resin layers at a wafer level, andfurthermore, a side surface and an upper surface of each of the resinlayers are formed to be a stepwise shape, so that warps of thesemiconductor wafer can be prevented even without using a resin layermaterial having special properties.

Also, since the film thickness of the resin layers stacked on thesurface other than the scribe line causes warps, the film thickness ofthe stacked resin layers can be made thicker compared with that in theconfiguration in which the scribe line is not removed. Namely, whenassuming that the film thickness per one layer is not changed, thenumber of resin layers to be stacked can be increased.

Also, when using resin layers having the same property values, warps ofthe wafer are reduced only by making the scribe line wide.

Furthermore, in the dicing step, only the semiconductor wafer is cut andit is not necessary to cut resin layers, so that it is not necessary toselect a special blade, either. Additionally, it is difficult for thesemiconductor wafer and the resin layers to come apart when dicing, andadjustment of the blade feeding speed becomes unnecessary. Accordingly,high throughput can be attained.

The present invention is not limited to the above explanation.

For example, while not described in the above production method of theembodiment, in the step of forming stacked resin layers and a wiringlayer on a boundary surface thereof, an electronic element and/or asemiconductor chip may be formed by being buried so as to beelectrically connected to a lower wiring layer.

In the above embodiment, four resin layers are stacked, but the numberof the layers is not limited to this; the stacked body may betwo-layered, three-layered, five-layered or more.

Also, between the semiconductor chip and the resin layers, a bufferlayer having an intermediate linear expansion coefficient of both may beprovided in accordance with need. The buffer layer is, for example,composed of an epoxy resin layer, etc. filled with filler.

Other than the above, a variety of modifications may be made within thescope of the present invention.

According to the semiconductor device of the present invention, in aSiP-type semiconductor device wherein an insulating layer is configuredby stacking a plurality of resin layers on a semiconductor chip, thelayer is configured so that formation areas of the plurality of resinlayers become gradually smaller from an area of the upper surface of thesemiconductor chip, and a side surface and an upper surface of each ofthe resin layers and the upper surface of the semiconductor chip form astepwise shape, so that a stress imposed on the semiconductor wafer issmall even in a stage before dicing and warps are suppressed.

According to the production method of the semiconductor device of thepresent invention, in a production method of a SiP-type semiconductordevice wherein an insulating layer is configured by a plurality of resinlayers stacked on a semiconductor chip, when forming by stacking thefirst resin layer and the second resin layer, except for the scribe linethat is to be a dicing region, the layers are formed so that their areasbecome gradually smaller from an area of an upper surface of thesemiconductor chip, and a side surface and an upper surface of each ofthe first resin layer and the second resin layer form a stepwise shape,and consequently, a stress imposed on the semiconductor wafer is smalleven in a stage before dicing and warps can be suppressed in producing asemiconductor device.

The semiconductor device of the present invention can be applied to asystem-in-package-type semiconductor device.

The production method of the semiconductor device of the presentinvention can also be applied for producing a system-in-package-typesemiconductor device.

What is claimed is:
 1. A semiconductor device, comprising: asemiconductor chip with a built-in electronic circuit, having electrodesformed on a surface thereof that are taken out from the electroniccircuit; an insulating layer formed of a plurality of resin layersstacked on the semiconductor chip; and a wiring layer formed so as to beelectrically connected to the electrodes and buried in the insulatinglayer; wherein the plurality of the resin layers is formed, so that asthe layers get farther from the semiconductor chip, their formationareas become gradually smaller from an area of an upper surface of thesemiconductor chip, and a side surface and an upper surface of each ofthe resin layers and the upper surface of the semiconductor chip form astepwise shape, wherein widths of exposed upper surfaces of the resinlayers at the stepwise shaped portion are 5 μm or more in the pluralityof the resin layers.
 2. The semiconductor device as set forth in claim1, wherein widths of exposed upper surfaces of the resin layers at thestepwise shaped portion are 5 μm or more in the plurality of the resinlayers.
 3. The semiconductor device as set forth in claim 1, whereinfurther comprising an electronic element and/or a another semiconductorchip are formed by being buried in the insulating layer so as to beelectrically connected to the wiring layer.
 4. A semiconductor device,comprising: a semiconductor chip with a built-in electronic circuit,having electrodes formed on a surface thereof that are taken out fromthe electronic circuit; an insulating layer formed of a plurality ofresin layers stacked on the semiconductor chip; and a wiring layerformed so as to be electrically connected to the electrodes and buriedin the insulating layer; wherein the plurality of the resin layers isformed, so that as the layers get farther from the semiconductor chip,their formation areas become gradually smaller from an area of an uppersurface of the semiconductor chip, and a side surface and an uppersurface of each of the resin layers and the upper surface of thesemiconductor chip form a stepwise shape, wherein an electronic elementand/or another semiconductor chip are formed by being buried in theinsulating layer so as to be electrically connected to the wiring layer.5. A semiconductor device, comprising: a semiconductor chip with abuilt-in electronic circuit, having electrodes formed on a surfacethereof that are taken out from the electronic circuit; an insulatinglayer formed of a plurality of resin layers stacked on the semiconductorchip; and a wiring layer formed so as to be electrically connected tothe electrodes and buried in the insulating layer; wherein the pluralityof the resin layers is formed, so that as the layers get farther fromthe semiconductor chip, their formation areas become gradually smallerfrom an area of an upper surface of the semiconductor chip, and a sidesurface and an upper surface of each of the resin layers and the uppersurface of the semiconductor chip form a stepwise shape, wherein theplurality of resin layers includes a first resin layer having a taperededge.
 6. The semiconductor device as set forth in claim 5, wherein: theplurality of resin layers includes a second resin layer, the secondresin layer have a smaller formation area than the first resin layer. 7.The semiconductor device as set forth in claim 6, wherein a ratio of athickness of the first resin layer to a distance, D₁, from an outer edgeof the first resin layer to an outer edge of the second resin layerbeing 2 or less.
 8. The semiconductor device as set forth in claim 6,wherein a distance from an outer edge of the first resin layer to anouter edge of the second resin layer being 5 μm or more.
 9. Thesemiconductor device as set forth in claim 5, wherein a distance from anoutermost edge of the semiconductor chip to an adjacent portion of thefirst resin layer being at least 10 μm.
 10. The semiconductor device asset forth in claim 9, wherein the distance from the outermost edge ofthe semiconductor chip to the adjacent portion of the first resin layerbeing at most 39 μm.
 11. The semiconductor device as set forth in claim6, wherein in at least one location, a film thickness of at least one ofthe first resin layer and the second resin layer being substantially 10μm.
 12. The semiconductor device as set forth in claim 5, wherein thefirst resin layer being at least one of polymide, epoxy and/or acrylic.13. The semiconductor device as set forth in claim 5, furthercomprising: a buffer layer disposed between the upper surface of thesemiconductor chip and the plurality of resin layers.
 14. Thesemiconductor device as set forth in claim 5, wherein an aggregatethickness of the plurality of resin layers for at least one portion ofthe plurality of layers is 50 μm or less.
 15. The semiconductor deviceas set forth in claim 5, wherein a length of at least one side surfaceof the semiconductor chip being 3 mm or less.
 16. The semiconductordevice as set forth in claim 5, further comprising: a seed layerdisposed between the wiring layer and the upper surface of thesemiconductor chip, and portions of the seed layer being in electricalcontact with portions of the wiring layer.
 17. The semiconductor deviceas set forth in claim 16, wherein the seed layer having a thickness ofin an inclusive range of 160 nm through 600 nm.
 18. The semiconductordevice as set forth in claim 7, wherein a distance from an outermostedge of the semiconductor chip to an adjacent portion of the first resinlayer being at least 10 μm.
 19. The semiconductor device as set forth inclaim 18, wherein the distance from the outermost edge of thesemiconductor chip to the adjacent portion of the first resin layerbeing at most 39 μm.
 20. The semiconductor device as set forth in claim19, further comprising: a buffer layer disposed between the uppersurface of the semiconductor chip and the plurality of resin layers. 21.The semiconductor device as set forth in claim 20, wherein an aggregatethickness of the plurality of resin layers for at least one portion ofthe plurality of layers is 50 μm or less.
 22. The semiconductor deviceas set forth in claim 21, further comprising: a seed layer disposedbetween the wiring layer and the upper surface of the semiconductorchip, and portions of the seed layer being in electrical contact withportions of the wiring layer.
 23. The semiconductor device as set forthin claim 22, wherein the seed layer having a thickness of in aninclusive range of 160 nm through 600 nm.
 24. The semiconductor deviceas set forth in claim 1, wherein: the plurality of resin layers includesa second resin layer, the second resin layer have a smaller formationarea than the first resin layer.
 25. The semiconductor device as setforth in claim 24, wherein a ratio of a thickness of the first resinlayer to a distance, D₁, from an outer edge of the first resin layer toan outer edge of the second resin layer being 2 or less.
 26. Thesemiconductor device as set forth in claim 1, wherein a distance from anoutermost edge of the semiconductor chip to an adjacent portion of thefirst resin layer being at least 10 μm.
 27. The semiconductor device asset forth in claim 26, wherein the distance from the outermost edge ofthe semiconductor chip to the adjacent portion of the first resin layerbeing at most 39 μm.
 28. The semiconductor device as set forth in claim27, further comprising: a buffer layer disposed between the uppersurface of the semiconductor chip and the plurality of resin layers. 29.The semiconductor device as set forth in claim 28, wherein an aggregatethickness of the plurality of resin layers for at least one portion ofthe plurality of layers is 50 μm or less.
 30. The semiconductor deviceas set forth in claim 29, further comprising: a seed layer disposedbetween the wiring layer and the upper surface of the semiconductorchip, and portions of the seed layer being in electrical contact withportions of the wiring layer.
 31. The semiconductor device as set forthin claim 30, wherein the seed layer having a thickness of in aninclusive range of 160 nm through 600 nm.
 32. The semiconductor deviceas set forth in claim 4, wherein: the plurality of resin layers includesa second resin layer, the second resin layer have a smaller formationarea than the first resin layer.
 33. The semiconductor device as setforth in claim 32, wherein a ratio of a thickness of the first resinlayer to a distance, D₁, from an outer edge of the first resin layer toan outer edge of the second resin layer being 2 or less.
 34. Thesemiconductor device as set forth in claim 4, wherein a distance from anoutermost edge of the semiconductor chip to an adjacent portion of thefirst resin layer being at least 10 μm.
 35. The semiconductor device asset forth in claim 34, wherein the distance from the outermost edge ofthe semiconductor chip to the adjacent portion of the first resin layerbeing at most 39 μm.
 36. The semiconductor device as set forth in claim35, further comprising: a buffer layer disposed between the uppersurface of the semiconductor chip and the plurality of resin layers. 37.The semiconductor device as set forth in claim 36, wherein an aggregatethickness of the plurality of resin layers for at least one portion ofthe plurality of layers is 50 μm or less.
 38. The semiconductor deviceas set forth in claim 37, further comprising: a seed layer disposedbetween the wiring layer and the upper surface of the semiconductorchip, and portions of the seed layer being in electrical contact withportions of the wiring layer.
 39. The semiconductor device as set forthin claim 38, wherein the seed layer having a thickness of in aninclusive range of 160 nm through 600 nm.